1. Field of the Invention
The present invention relates to a semiconductor light emitting device, and more particularly, to a semiconductor light emitting device, in which a plurality of light emitting cells are arranged, and a method for manufacturing the same.
2. Description of the Related Art
In general, semiconductor light emitting diodes (LEDs) are advantageous for light sources in terms of power, efficiency and reliability. Therefore, semiconductor LEDs are being actively developed as high-power, high-efficiency light sources for various illumination apparatuses as well as for a backlight unit of a display device. For the commercialization of such semiconductor LEDs as illumination light sources, it is necessary to increase their efficiency and reduce their production cost while increasing their power to a desired level.
However, a high-power LED using a high rated current may have low light efficiency due to a high current density, when compared to a low-power LED using a low-rated current. Specifically, if a rated current is increased to obtain high luminous flux in an LED chip of the same area in order to obtain high power, the light efficiency may be degraded due to an increase in the current density. Also, the light efficiency degradation is accelerated due to heat generation by the device.
To solve these problems, there has been proposed a high-power light emitting device in which a plurality of low-power LED chips are die-bonded at a package level and the chips thereof are connected by wire bonding. According to this approach, since the low-power LED chips having a relatively small size are used, current density is further reduced and thus an overall light efficiency is increased, as compared to a case of using high-power LED chips having a large size. However, as the number of wire bondings increases, manufacturing costs increase and manufacturing processes become complicated. In addition, a fail rate due to a wire open condition increases. When the chips are connected by wires, it is difficult to implement a complicated serial-parallel interconnection structure. Due to the space occupied by the wires, it is difficult to achieve the miniaturization of the package. Moreover, there is a limit on the number of chips which are mountable in a single package.